1. Field of the Invention
This invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and particularly to technology for controlling the formation of impurity-doped regions in a semiconductor layer by a method of working a gate electrode of the device by dry etching. The invention can for example be applied to displays wherein this semiconductor device is used in a display part, and particularly to liquid crystal displays, organic EL displays (a light emitting device or a light emitting diode) and electronic equipment using such displays. The EL (electroluminescent) devices referred to in this specification include triplet-based light emission devices and/or singlet-based light emission devices, for example.
2. Description of the Related Art
When in the fabrication of a semiconductor device a semiconductor layer is formed by dry etching or wet etching, or when an impurity region is formed in a semiconductor layer by doping, a mask made of photoresist is used.
In dry etching or wet etching, the material outside the part covered by the mask is removed, and the material which is not etched assumes the same shape as the shape of the mask.
When doping is carried out, an impurity region is formed in the part of the semiconductor layer which is not covered by the mask.
In recent years, the microminiaturization of structures of semiconductor devices having thin film transistors (hereinafter, TFTs) has been progressing. Consequently, there has been a need for finer positioning in mask formation. Insufficiently fine positioning is a cause of formation defects in the forming of resist masks. There has been known a method whereby to overcome this a semiconductor device is fabricated by a part of a TFT (for example the gate electrode) being formed by dry etching and then other parts of the TFT (for example source and drain regions) being formed using this already-formed part of the TFT (for example the gate electrode) as a mask, self-aligningly.
With such a method for making a semiconductor device self-aligningly it is possible to realize a reduction in the number of photo masks used in the forming of photoresist masks by photolithography, and fine positioning is unnecessary. Because of this, the technology is currently receiving attention.
For the forming of an impurity region in a semiconductor layer, the method of doping the semiconductor layer with a group 15 (of the periodic table) impurity element such as phosphorus or arsenic or a group 13 (of the periodic table) impurity element such as boron is used.
Doping a semiconductor layer with a group 15 impurity element forms an n-type region, and doping with a group 13 impurity element forms a p-type region, and in this way source and drain regions are formed in a semiconductor layer.
A characteristic of a TFT is its OFF current (the current which flows through the channel region when the TFT is OFF; in this specification, Ioff). When the characteristics of a TFT are being evaluated, it is desirable that the value of this Ioff be small.
To make Ioff small, it is beneficial to form an LDD (Lightly Doped Drain) region in the part of the semiconductor layer positioned outside the gate electrode.
Also, if hot carriers arise in the channel region when the TFT is being driven (i.e. is ON), this causes the semiconductor device to deteriorate. To prevent this, it is desirable that a second LDD region be formed in a part of the semiconductor layer overlapping with the gate electrode.
A semiconductor device structure having an LDD region overlapping with the gate electrode across a gate insulating film is known as a GOLD (Gate-drain Overlapped LDD) structure.
GOLD structures are also called LATID (Large-tilt-angle implanted drain) structures and ITLDD (Inverse TLDD) structures. For example in ‘Mutsuko Hatano, Hajime Akimoto and Takeshi Sakai, IEDM97 TECHNICAL DIGEST, P 523-526, 1997’ it is confirmed that a GOLD structure with a silicon side wall provides extremely good reliability compared to other TFT structures.
In the fabrication of a semiconductor device having a TFT, the forming of a mask from photoresist necessitates many steps beforehand and afterward. These include for example substrate washing; the application of resist material; pre-baking; exposing; developing; and post-baking.
And the photoresist mask must be removed after the etching or doping process, and numerous steps are also required for this removal. These include for example ashing with a gas selected from among O2, H2O and CF4; removal using chemicals; or removal by means of a combination of ashing and chemical treatment. At this time, removal using chemicals necessitates steps such as chemical treatment; rinsing with pure water; and drying of the substrate.
Thus there has been the problem that using masks made from photoresist increases the number of steps required to make a semiconductor device.
And, along with the microminiaturization of semiconductor devices, finer positioning in mask formation has been required. Insufficiently fine positioning is a cause of formation defects of resist masks, as mentioned above, and time spent repairing such defects results in increased process time and has been a cause of increased manufacturing costs.
The use of masks made from photoresist in the fabrication of semiconductor devices has thus increased the number of steps required for the fabrication process; increased the time required to complete the steps; increased manufacturing costs; and affected product yield.
Accordingly, reducing the number of masks used is an effective way of reducing the manufacturing cost of a semiconductor device.
Also, when the characteristics of a TFT in a semiconductor device are considered, it is desirable that a first LDD region of the kind mentioned above be formed in the semiconductor layer, as this is effective in reducing Ioff, which is an important characteristic of a TFT.
And to prevent deterioration of the semiconductor device it is preferable for the device to have a GOLD structure, and by forming a second LDD region of the kind described above so as to overlap with the gate electrode across the gate insulating film it is possible to suppress hot carriers forming in the channel region and the drain region.
In this specification document the above-mentioned first LDD region will be called the Loff region and the above-mentioned second LDD region will be called the Lov region.
However, to dope the Loff region and the Lov region with an impurity it has been necessary in each case to form a mask made of photoresist on the semiconductor layer, and the increase in the number of steps resulting from the increase in the number of masks needed has been a problem.
And, in a semiconductor device having a GOLD structure wherein the edge of the gate electrode is positioned on the gate insulating film above the boundary between the Loff region and the Lov region, fine positioning is necessary in the formation of the photoresist masks, and the process has been complicated. Consequently, trouble has often arisen which causes positioning failure at the time of mask formation.
For these reasons, in the forming of a semiconductor device having a GOLD structure, because the structure necessitates fine positioning control, increased numbers of masks and trouble in the formation of photoresist masks have been a great problem and have constituted a cause of increased manufacturing cost of the semiconductor device, increased time required for manufacture, and reduced manufacturing yield.
To overcome this, the present inventors, having been researching the possibility of forming an Loff region and an Lov region to constitute LDD regions of a semiconductor device having a GOLD structure self-aligningly without using masks made from photoresist, have invented a fabrication method for forming an Loff region and an Lov region by doping a semiconductor layer with an impurity element self-aligningly by means of certain gate electrode materials and dry etching methods.
By using this invention it is possible to form an Loff region and an Lov region by doping the semiconductor layer with an impurity element self-aligningly and thereby to reduce the number of masks required and eliminate trouble associated with the formation of these masks. Thus it is possible to reduce the manufacturing cost of a semiconductor device and the time required for its manufacture.